The present invention relates to a memory system (and method of using same) wherein relatively complex operations may be performed.
Network computer systems generally include a plurality of geographically separated or distributed computer nodes that are configured to communicate with each other via, and are interconnected by, one or more network communications media. One conventional type of network computer system includes a network storage subsystem that is configured to provide a centralized location in the network at which to store, and from which to retrieve data. Advantageously, by using such a storage subsystem in the network, many of the network""s data storage management and control functions may be centralized at the subsystem, instead of being distributed among the network nodes.
One type of conventional network storage subsystem, manufactured and sold by the Assignee of the subject application (hereinafter xe2x80x9cAssigneexe2x80x9d) under the trade name Symmetrix(trademark) (hereinafter referred to as the xe2x80x9cAssignee""s conventional storage systemxe2x80x9d), includes a plurality of disk mass storage devices configured as one or more redundant arrays of independent (or inexpensive) disks (RAID). The disk devices are controlled by disk controllers (commonly referred to as xe2x80x9cback endxe2x80x9d controllers/directors) that store user data in, and retrieve user data from a shared cache memory resource in the subsystem. A plurality of host controllers (commonly referred to as xe2x80x9cfront endxe2x80x9d controllers/directors) may also store user data in, and retrieve user data from, the shared cache memory resource. The disk controllers are coupled to respective disk adapters that, among other things, interface the disk controllers to the disk devices. Similarly, the host controllers are coupled to respective host channel adapters that, among other things, interface the host controllers via channel input/output (I/O) ports to the network communications channels (e.g., Small Computer Systems Interface (SCSI), Enterprise Systems Connection (ESCON), and/or Fibre Channel (FC) based communications channels) that couple the storage subsystem to computer nodes in the computer network external to the subsystem (commonly termed xe2x80x9chostxe2x80x9d computer nodes or xe2x80x9chostsxe2x80x9d).
In the Assignee""s conventional storage system, the shared cache memory resource may comprise a plurality of memory circuit boards that may be coupled to an electrical backplane in the storage system. The cache memory resource is a semiconductor memory, as distinguished from the disk storage devices also comprised in the Assignee""s conventional storage system, and each of the memory boards comprising the cache memory resource may be populated with, among other things, relatively high-speed synchronous dynamic random access memory (SDRAM) integrated circuit (IC) devices for storing the user data. The shared cache memory resource may be segmented into a multiplicity of cache memory regions. Each of the regions may, in turn, be segmented into a plurality of memory segments.
Computer programs may include instruction loops comprising respective sets of instructions that may be repetitively executed in a plurality of respective iterations. The execution of an iteration of a set of loop instructions may be conditioned upon whether a respective control variable value (e.g., a loop counter value) stored in the cache memory resource satisfies one or more predetermined arithmetic and/or logical relationships involving that value. Additionally, each time a determination is made as to whether to execute an iteration of a set of loop instructions, it is typically necessary to change (e.g., increment/decrement) the stored value of the associated control variable.
When a determination is to be made as to whether such a control variable value satisfies an associated predetermined relationship, a set of related operations (hereinafter termed xe2x80x9cthe related operationsxe2x80x9d) may be performed in the Assignee""s conventional storage system. The set of related operations may include (1) retrieving (e.g., to a host or disk controller) from the cache memory system the value of that control variable that is presently stored in the cache memory resource (hereinafter termed xe2x80x9cthe present control variable valuexe2x80x9d), (2) performing one or more arithmetic and/or logical calculations using the retrieved control variable value for the purpose of determining whether the present control variable value satisfies the associated predetermined relationship, and (3) overwriting the present control variable value stored in the cache memory resource with an updated control variable value.
The cache memory resource in the Assignee""s conventional storage system is configured to carry out relatively simple read-modify-write operations, based upon commands received from a host or disk controller, that may be used to facilitate at least some of these related operations. For example, the cache memory resource may be configured to perform a read-modify-write operation that may increment or decrement the present control variable value to generate the updated control variable value, and may overwrite the present control variable value stored in the cache memory resource with the updated control variable value. Other examples of such relatively simple read-modify-write operations may read a first data value from the cache memory resource, perform a logical XOR, AND, or OR of the first data value with a second data value supplied from a host/disk controller, and store the results thereof in the memory location from which the first data value was read.
It would be desirable to enhance the utility, versatility, and effectiveness of the cache memory resource by providing in the cache memory resource means for carrying out one or more improved read-modify-write operations that involve relatively more complex arithmetic and/or logical operations than those that may be performed by the cache memory resource in the Assignee""s conventional storage system. It would also be is desirable to minimize the number of cache memory resource data transfer cycles (and also, therefore, the time) required to carry out these improved read-modify-write operations.
In accordance with the present invention, a memory system and method of using same are provided, wherein means are provided for carrying out one or more improved read-modify-write operations, executed atomically, that involve arithmetic and/or logical operations of greater complexity than those that may be carried out in the aforesaid prior art. The memory system of the present invention may be a shared cache memory resource that may include at least one memory region that may store data, and at least one logic section. The at least one logic section may be used to facilitate the execution of the one or more respective atomic read-modify-write memory operations during one or more respective data transfer cycles of the memory system.
In one embodiment of the present invention, the at least one logic section may include a plurality of different types of logic sections, and the at least one memory region may include a plurality of memory regions. Each of these logic sections may be used independently to facilitate the execution of a respective atomic read-modify-write memory operation during a respective data transfer cycle, and may be associated with a respective one of the plurality of memory regions.
The memory system may include one or more electrical circuit boards, and the memory regions and the logic sections may be comprised in the one or more electrical circuit boards. The different types of logic sections that may be comprised in the memory system according to this embodiment of present invention are described more fully below.
A first type of logic section (hereinafter termed xe2x80x9cthe first logic sectionxe2x80x9d) may be used to facilitate the respective execution, during a respective data transfer cycle of the memory system, of a first type of atomic read-modify-write operation that may perform an addition operation that sums together a first complete data word, read from a memory region with which the first logic section is associated, and a second complete data word from an external device (e.g., an I/O controller, such as a host/disk controller). The first complete data word may be retrieved from this memory region and may be received by the first logic section during this respective data transfer cycle; the second complete data word also may be received by the first logic section from the external device during the respective data transfer cycle. The respective first type of atomic read-modify-write operation also may include transmitting to the external device the first complete data word.
A second type of logic section (hereinafter termed xe2x80x9cthe second logic sectionxe2x80x9d) may be used to facilitate the execution, during a respective data transfer cycle of the memory system, of a respective second type of atomic read-modify-write operation that may perform a plurality of arithmetic operations involving portions of a respective first data word, read from a memory region with which the second logic section is associated, and portions of a respective second data word from the external device (i.e., host/disk controller). The portions of the respective first data word may be retrieved from this memory region and also may be received by the second logic section during this respective data transfer cycle; the portions of the respective second data word may be received by the second logic section from the external device during this respective data transfer cycle. The respective second type of atomic read-modify-write operation may also include transmitting to the external device the first data word.
In the second logic section, the arithmetic operations may comprise a first addition operation and a second addition operation. The first addition operation may add a low order portion of the respective first data word to a low order portion of the respective second data word. The second addition operation may add a remaining portion of the respective first data word to a remaining portion of the respective second data word.
In a third type of logic section (hereinafter termed xe2x80x9cthe third logic sectionxe2x80x9d) whose operating principles are similar to those of the second logic section, the respective first and second data words may each comprise N respective bytes, where N may be a positive integer. The arithmetic operations may comprise N addition operations and each of the N addition operations may add one respective byte from the respective first data word to another respective byte from the respective second data word. The one respective byte and the other respective byte may have respective corresponding orders.
In a fourth type of logic section (hereinafter termed xe2x80x9cthe fourth logic sectionxe2x80x9d) whose operating principles may be similar to those of the second logic section, the respective first and second data words may each comprise N respective double-bytes (i.e., 16-bit terms), where N may be a positive integer. Each double-byte may have two respective bytes, and the arithmetic operations may comprise N addition operations. Each of these N addition operations may add one respective double-byte from the respective first data word to another respective double-byte from the respective second data word. The one respective double-byte and the other respective double-byte may have respective corresponding orders.
A fifth type of logic section (hereinafter termed xe2x80x9cthe fifth logic sectionxe2x80x9d) may be used to facilitate the execution, during a respective data transfer cycle of the memory system, of an additional type of atomic read-modify-write operation that may involve a respective first data word, a respective second data word, a respective third data word, and a respective fourth data word. The respective first data word may be from a location in a memory region with which the fifth logic section may be associated. The respective second data word may be from the external device (i.e., host/disk controller). The respective first data word may be retrieved from the memory region, and may be received by the third logic section during the respective data transfer cycle; the respective second data word may be received by the third logic section from the external device during the respective data transfer cycle.
This additional type of atomic read-modify-write operation may also comprise transmitting to the external device the respective first data word, and comparing the respective third data word to the respective fourth data word. If the respective third data word matches the respective fourth data word, this additional type of atomic read-modify-write operation also may include storing in the memory location from which the respective first data word was retrieved one or more selected portions of the respective second data word.
The fifth logic section may include masking logic that may be used to select these one or more selected portions of the respective second data word. The masking logic may comprise a first AND logic section that may receive the respective second data word and a respective fifth data word. The fifth data word may be supplied from the external device. The masking logic may also comprise a second AND logic section that may receive the respective first data word and an inversion of the respective fifth data word, and an OR logic section that may receive respective outputs from the first and second AND logic sections.
In the fifth logic section, the respective third data word may be generated by a third AND logic section that may receive the respective first data word and a comparison mask. Also in the fifth logic section, the respective fourth data word may be generated by a fourth AND logic section that may receive a comparison data word and the comparison mask.
Advantageously, the improved read-modify-write operations provided in accordance with the present invention permit the utility, versatility, and effectiveness of the memory system of the present invention to be enhanced compared to the prior art. Also advantageously, each improved read-modify-write operation according to the present invention may be carried out in a single respective data transfer cycle, and thus, the number of data transfer cycles (and also, therefore, the time) required to carry out each such operation may be minimized.